Delay optimization of carry-skip adders and block carry-lookahead adders

The worst-case carry propagation delays in carryskip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. We report on a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do not guarantee a minimum latency configuration. Under our delay model, critical path delay is calculated not only taking into account the intrinsic gate delays, but also the fanin and fanout contributions.